1. Field of the Invention
This invention relates to the method of manufacturing semiconductor devices and more particularly to the method of manufacturing an electrically isolated region of buried groove type between circuit elements.
2. Description of the Related Art
The well known methods of electrically isolating from one another the circuit elements such as transistors used in semiconductor devices include a PN junction isolation which makes use of the PN junction, an oxide isolation which selectively oxides regions between circuit elements and a trench isolation which forms trenches in the semiconductor substrate and fills the trenches with an insulating material. Of these methods, the trench isolation is finding a greater use because of its ability to define small sizes of isolated regions and at the same time provide a more reliable electrical isolation, contributing to increasing the circuit density of the semiconductor devices. A bipolar device to which the trench isolation method is applied is illustrated, for example, in FIG. 1 of 1982 IEEE International Solid-State Circuits Conference/FRIDAY, FEB. 12, l982/SESSION XVII: DEVICE STRUCTURES AND TECHNOLOGY "FAM l7.6:l.25.mu.m Deep-Groove-Isolated Self-Aligned ECL Circuits." In FIG. 1 the isolation grooves of different depths are filled with insulating material in such a manner that the surfaces of the buried insulating material are flat. However, no technique has been proposed as to the method of manufacturing such an isolation structure which has flat surfaces of the insulating material and which can increase circuit density.
Especially when insulating material is to be buried in trenches (grooves) of different depths, as shown in the above technical literature, the insulating material may not be buried in a satisfactory condition due to steps formed at the bottom of the trenches. This may result in poor isolation performance or insufficient surface flatness of the buried insulating material, which in turn may cause a break of the upper electric wiring on the surface. Another problem is that in a relatively wide isolation region, the insulating film formed in this region is relatively thin, so that a larger parasitic capacitance is formed between the upper electric wiring and the substrate silicon layer via the insulating film, reducing the operation speed of the semiconductor device.